1. Field of Invention
The present invention relates to a method for manufacturing integrated circuits. More particularly, the present invention relates to a method for manufacturing polysilicon load of a static random access memory (SRAM) that facilitates the reduction of device dimensions and an increase in the level of integration.
2. Description of Related Art
Static random access memories (SRAMs) are now extensively used in integrated circuits, especially in the telecommunication and electronic industries. Therefore, how to reduce device dimensions, how to increase the level of integration without compromising the quality are some of the major goals in the production industry. Polysilicon loads are one of the basic elements in a SRAM cell. The polysilicon loads serve as resistor in the circuit, which are normally formed by doping very low concentration of ions or not doping ions on a line segment of a polysilicon line. On the other hand, interconnects are formed on the same polysilicon lines by specifically doping a heavier concentration of ions on a particular line segment.
FIG. 1 is a circuit layout diagram of a conventional four-transistor static random access memory (4T SRAM). As shown in FIG. 1, R.sub.1 and R.sub.2 are load resistors, and M.sub.1 and M.sub.2 are enhancement mode NMOS transistors that function as drivers. Furthermore, enhancement mode NMOS M.sub.3 and M.sub.4 are used for accessing data contained in the SRAM. The gates of transistor M.sub.3 and M.sub.4 are controlled by a horizontal conductive line referred to as a word line (WL). The source terminals of M.sub.3 and M.sub.4 are connected to transistor drivers M.sub.l and M.sub.2, respectively. Therefore, the ON and OFF state of the transistors M.sub.l and M.sub.2 are closely related to the switching states of transistors M.sub.3 and M.sub.4. The source terminals of M.sub.3 and M.sub.4 are each connected to a vertical conducting line referred to as a bit line (BL).
In general, for the 4T SRAM, the same polysilicon layer is used to form interconnects and loads. To form an interconnect, the desired segment on the polysilicon line is heavily doped, and to form a load, the desired segment on the polysilicon line is lightly doped or not doped at all. Since the loads and the interconnects are formed on the same polysilicon lines in a conventional production method, thickness of both the interconnect lines and the load lines are almost the same.
FIG. 2 is a cross-sectional view showing a conventional polysilicon load structure. As shown in FIG. 2, a gate polysilicon element 12 and a power line polysilicon element 14 is formed over a substrate 10. Then, an insulating layer 16 is deposited over the substrate 10. This is followed by etching the insulating layer 16 to form contact window 17a that exposes the gate polysilicon element 12, and contact window 17b that exposes the power line polysilicon element 14. Thereafter, a polysilicon layer is formed over the insulating layer 16 and into the contact windows 17a and 17b. Subsequently, an ion doping operation using a low ion concentration level is performed to form a polysilicon load line in segment 18. Next, a second ion doping operation is performed, this times using a higher ion concentration level to form the interconnects in area 20a and 20b.
In general, the conventional method of producing a high load resistance is by decreasing the thickness of polysilicon layer, increasing the length of the polysilicon load line, or reducing the width of the polysilicon load line. However, when the SRAM cells are further miniaturized, the aforementioned method of using the same polysilicon layer to fabricate interconnects and loads by variation the doping concentrations on different polysilicon line segments in two doping operations becomes infeasible. The main reason is that during subsequent thermal processing operations, the large amount of doped impurities from the second implant will out-diffuse from the interconnects and reduce the effective length of the polysilicon load line. Thus, the resistance of the load line will be lowered and the current flow in them will increase. Furthermore, the diffusion of ions will lead to difficulties in controlling the quality of the product. This is an especially difficult problem for the conventional method. Because, if we want to extend the length of the polysilicon load line, there is no more space due to the miniaturization of memory cells. On the other hand, if the load resistance is increased through reducing the width of a polysilicon load line, it is difficult to avoid increasing the resistance of the interconnect as well. This is because the interconnects and the loads are formed along the same polysilicon line. Therefore, the conventional method of forming the polysilicon load line is a major limitation for the miniaturization of the memory cells.
In light of the foregoing, there is a need in the art to provide an improved method of manufacturing polysilicon load for SRAM cells.